1. Field of the Invention
The present invention relates to a semiconductor device having a decoupling condenser.
2. Description of the Background Art
As one way to miniaturize semiconductor devices, a technique called xe2x80x9cchemical mechanical polishingxe2x80x9d(hereinafter, referred to as xe2x80x9cCMPxe2x80x9d) has conventionally been employed. In the CMP process, a surface of an interlayer insulating film or the like on a semiconductor substrate is polished for planarization to improve precision in photolithography in a subsequent process. This technique, however, has the following disadvantages. The surface of the interlayer insulating film may be polished excessively over an area where pattern density of gate electrodes or the like within the semiconductor chip is sparse, whereas it may be polished unsatisfactorily over an area with high pattern density. This creates an asperity on the surface of the interlayer insulating film. To prevent such an asperity, the variation in the pattern density of gate electrodes or the like to be formed on the semiconductor substrate should be reduced. To this effect, the area with sparse pattern density has been provided with dummy patterns, e.g., dummy gate electrodes, that are unnecessary for a circuit operation.
A structure of a semiconductor device having dummy patterns for use in the conventional CMP process will now be described with reference to FIGS. 16 to 19. As shown in FIGS. 17 and 19, a pxe2x88x92 well 123 and an nxe2x88x92 well 119 are formed below a main surface of a semiconductor substrate with a prescribed depth. In respective regions of pxe2x88x92 well 123 and nxe2x88x92 well 119, as shown in FIGS. 16 and 18, element forming regions are formed, separated from one another by an isolating insulating film 135. P+ and n+ impurity regions are formed in the element forming regions.
The p+ and n+ impurity regions in pxe2x88x92 well 123 and nxe2x88x92 well 119 are connected with contact plugs 140 and 145, respectively. Contact plugs 140 are connected with a ground electrode (GND) interconnection line 114, and thus, pxe2x88x92 well 123 has a potential fixed by the ground electrode. Contact plugs 145 are connected with a power supply electrode (Vcc) interconnection line 113, whereby nxe2x88x92 well 119 has a potential fixed by the power supply electrode. In prescribed regions where the surfaces of pxe2x88x92 well 123 and nxe2x88x92 well 119 are exposed, gate insulating film dummy patterns 121a and 129a are formed, respectively, in the same layer as gate insulating films 121 and 129. Gate electrode dummy patterns 131a and 139a are formed in the same layer as gate electrodes 131 and 139.
In the semiconductor device having dummy patterns formed for use in the above-described conventional CMP process, gate electrode dummy patterns 131a and 139a formed in the gate electrode forming process are stacked on top of gate insulating film dummy patterns 121a and 129a formed in the gate insulating film forming process, respectively, as shown in FIGS. 16 and 17. Here, the gate electrode dummy patterns, which are floating conductive layers, induce parasitic capacitance, for which no countermeasures are taken. To lessen the adverse effects that such uncontrolled parasitic capacitance because of the floating conductive layers would pose on the electronic circuit, gate electrode dummy patterns 131a, 139a are disposed on isolating insulating film 135 in some cases, as shown in FIGS. 18 and 19.
FIG. 20 is a general equivalent circuit diagram of the conventional semiconductor device as described above. As shown in FIG. 20, the conventional semiconductor device has a circuit configuration in which elements are successively connected as follows. An external power supply electrode (Vcc) interconnection line 101 is connected to a power supply electrode (Vcc) pin 102. Power supply electrode (Vcc) pin 102 is connected to a power supply electrode (Vcc) pad 103. An external ground electrode (GND) interconnection line 104 is connected to a ground electrode (GND) pin 105. Ground electrode (GND) pin 105 is connected to a ground electrode (GND) pad 106. Electronic circuits 108 are connected in parallel with each other between power supply electrode (Vcc) pad 103 and ground electrode (GND) pad 106.
A parasitic inductance 120 of power supplying lead frame is formed between external power supply electrode (Vcc) interconnection line 101 and power supply electrode (Vcc) pin 102, and also between external ground electrode (GND) interconnection line 104 and ground electrode (GND) pin 105. A parasitic inductance 130 of bonding wire is formed between power supply electrode (Vcc) pin 102 and power supply electrode (Vcc) pad 103 and also between ground electrode (GND) pin 105 and ground electrode (GND) pad 106. Parasitic resistances 107 are formed on interconnection lines connecting power supply electrode (Vcc) pad 103 and electronic circuits 108, and on interconnection lines connecting ground electrode (GND) pad 106 and electronic circuits 108.
In the conventional semiconductor device as described above, electric fields are generated in parasitic inductance 120 of the lead frame and in parasitic inductance 130 of the bonding wire, in a direction to prevent an abrupt change of current. Therefore, there occur a drop of the potential of power supply electrode (Vcc) pad 103, and an increase of the potential of ground electrode (GND) pad 106, as expressed by the following equation (1).
xcex94Vxc3x97L=dI/dtxe2x80x83xe2x80x83(1)
wherein xcex94V is a potential difference;
L is an inductance;
I is a current; and
t is a time.
There also occur local potential drop and increase within the semiconductor chip due to the parasitic resistance, as expressed by the following equation (2).
xcex94V=Ixc3x97Rxe2x80x83xe2x80x83(2)
wherein xcex94V is a potential difference;
I is a current; and
R is a resistance.
The operating voltage of the semiconductor device should be set taking into consideration the potential drop in power supply electrode (Vcc) pad 103 and the potential increase in ground electrode (GND) pad 106 as described above. This hinders reduction of the operating voltage of the semiconductor device.
Furthermore, noise is generated due to the abrupt change in the current flowing from one circuit to another circuit via the power supplying lead frame and the bonding wire, as expressed by equation (1). This causes electromagnetic waves to be emitted outwards from the semiconductor device. Such electromagnetic waves induce electromagnetic interference (EMI) in neighboring components of the semiconductor device.
One way of suppressing the local potential drop and increase within the circuits as well as the EMI between the semiconductor device and its neighboring components as described above is to provide the semiconductor device with a decoupling condenser. Providing a region dedicated to the decoupling condenser, however, will lead to an increase in an area required for the semiconductor device.
An object of the present invention is to provide a semiconductor device operable under a low voltage with suppressed EMI, by utilizing dummy patterns used in the above-described CMP process, without increasing the area occupied by the semiconductor device.
The semiconductor device according to the present invention is a semiconductor device having an electronic circuit and a decoupling condenser provided in parallel with each other between a power supply electrode and a ground electrode, wherein the electronic circuit includes a transistor. The decoupling condenser includes: an impurity region formed below a main surface of a semiconductor substrate with a prescribed depth; a dummy gate insulating film located on the impurity region, formed in the same layer as a gate insulating film of the transistor; and a dummy gate electrode located on the dummy gate insulating film, formed in the same layer as a gate electrode of the transistor.
According to the structure as described above, the decoupling condenser is formed in parallel with the electronic circuit having the transistor. Therefore, the electronic circuit having the transistor can be charged instantly with the charges stored in the decoupling condenser when the power supply potential drops or the ground potential increases due to a switching operation of a neighboring electronic circuit. This can suppress generation of power supply noise that would pose adverse effects on the electronic circuit having the transistor. Accordingly, malfunction of the electronic circuit can be prevented even when the operating voltage is set small. As a result, it is possible to decrease the lower limit of the operating voltage of the semiconductor device.
It is also possible to enclose any abrupt current change within the power supply line of each electronic circuit. Therefore, it is possible to avoid an event in which a noise generated in one electronic circuit enters another electronic circuit via the bonding wire connecting the electrode pad and the power supply electrode pin. In other words, a large current change in the power supplying system can be suppressed. This leads to reduction in electromagnetic waves emitted outwards from the semiconductor device, and as a result, EMI in the neighboring components of the semiconductor device is suppressed.
Moreover, according to the structure as described above, the decoupling condenser is formed with a dummy gate insulating film and a dummy gate electrode which are dummy patterns for use in the CMP process formed in the same layers as a gate insulating film and a gate electrode, respectively. Normally, the dummy gate insulating film and the dummy gate electrode are disposed thoroughly in regions on the semiconductor substrate where no gate electrodes are formed, such that the surface of the interlayer insulating film can be planarized in the CMP process therefor. This means that the decoupling condenser can be formed without occupying a special region dedicated thereto on the semiconductor substrate. As a result, it becomes possible to prevent the malfunction under a low voltage as well as the EMI, while reducing an area occupied by the semiconductor device.
Preferably, in the semiconductor device according to the present invention, the ground electrode includes a first ground electrode pad connected to a prescribed analog circuit and a second ground electrode pad connected to an electronic circuit other than the prescribed analog circuit, and the power supply electrode includes a first power supply electrode pad connected to the prescribed analog circuit and a second power supply electrode pad connected to the electronic circuit other than the prescribed analog circuit.
With the structure as described above, a prescribed analog circuit and an electronic circuit other than the prescribed analog circuit are separated from each other in parallel, from their power supply electrode pads to their ground electrode pads. Therefore, when the power supply potential drops or the ground potential rises, noise generated will be transmitted both ways between the prescribed analog circuit and the electronic circuit other than the prescribed analog circuit via parasitic inductance of the bonding wire, i.e., via parasitic inductance of the bonding wire connecting the power supply electrode pad and a power supply electrode pin provided outside of the power supply electrode pad, and via parasitic inductance of the bonding wire connecting the ground electrode pad and a ground electrode pin provided outside of the ground electrode pad.
Such parasitic inductance suppresses an abrupt change in the current. Therefore, the noise generated in an electronic circuit other than the prescribed analog circuit is prevented from being transmitted to the analog circuit, in which such a noise would normally cause malfunction. In other words, the noise can be enclosed within the electronic circuit other than the prescribed analog circuit more effectively. As a result, the malfunction of the prescribed analog circuit affected by the noise generated in the electronic circuit other than the prescribed analog circuit can be prevented more reliably.
More preferably, in the semiconductor device according to the present invention, the ground electrode includes a first ground electrode pin connected to the first ground electrode pad and a second ground electrode pin connected to the second ground electrode pad, and the power supply electrode includes a first power supply electrode pin connected to the first power supply electrode pad and a second power supply electrode pin connected to the second power supply electrode pad.
With such a structure, a prescribed analog circuit and an electronic circuit other than the prescribed analog circuit are separated from each other in parallel, from the power supply electrode pins to the ground electrode pins. Therefore, there exist parasitic inductances of the bonding wire between the power supply electrode pad and the power supply electrode pin and between the ground electrode pad and the ground electrode pin in each of the prescribed analog circuit and the electronic circuit other than the prescribed analog circuit, and there also exists parasitic inductance of the lead frame outside of each of the power supply electrode pin and the ground electrode pin. Thus, the noise generated in the electronic circuit other than the prescribed analog circuit passes through two inductances, i.e., the parasitic inductance of the bonding wire and the parasitic inductance of the lead frame. As a result, enclosure of the noise can further be assured. In other words, when the power supply potential drops or the ground potential increases, the transmission of the noise generated in the electronic circuit other than the prescribed analog circuit to the prescribed analog circuit can be prevented with additional reliability.
In the semiconductor device according to the present invention, the impurity region may be a p type impurity region electrically connected to the ground electrode, and the dummy gate electrode may be electrically connected to the power supply electrode.
Further, in the semiconductor device according to the present invention, the impurity region may be an n type impurity region electrically connected to the power supply electrode, and the dummy gate electrode may be electrically connected to the ground electrode.
More preferably, in the semiconductor device according to the present invention, the impurity region includes an element forming region isolated by an element isolating region, and a field dummy region being a dummy pattern of the element forming region, wherein a semiconductor element is formed in the element forming region, and the dummy gate insulating film and the dummy gate electrode are formed in the field dummy region.
With such a structure, the element forming region in which the semiconductor element is to be formed and the field dummy region which is to be one electrode of the decoupling condenser are formed in one impurity region. Accordingly, two connections, i.e., the connection between the one electrode of the decoupling condenser and the ground or power supply electrode, and the connection between the ground or power supply electrode and a well for fixing the potential so as to stabilize the operation of the semiconductor element, can be realized simply by connecting one contact plug with one impurity region. As a result, in a region proximate to the decoupling condenser, it is only necessary to form either an interconnection line for connection of the dummy gate electrode of the decoupling condenser with the ground electrode, or an interconnection line for connection of the dummy gate electrode of the decoupling condenser with the power supply electrode. This increases the degree of freedom in layout design. As a result, it is possible to reduce the layout area of the semiconductor device.